The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a floating gate memory cell, i.e., an erasable programmable read-only memory (EPROM) cell, that is fabricated utilizing a vertical transistor processing flow.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar defines the channel with the source and drain located at opposing ends of the semiconductor pillar. One advantage of a vertical transistor is that the channel length is not defined by lithography, but by methods such as epitaxy or layer deposition, which enable precise dimensional control. As such, vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
An EPROM, or erasable programmable read-only memory, is one type of flash memory that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile. An EPROM is an array of floating gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to a strong ultraviolet light source (such as from a mercury-vapor light). In typical EPROM cells, the floating gate transistors are formed utilizing non-vertical transistor technology. In view of the advantages with vertical transistor designs, there is a need for providing a floating gate memory (i.e., EPROM cell) using vertical transistor technology.